Pipeline analog to digital converters (ADC) are known to be useful for high speed and high resolution conversion of analog signals to digital format. A pipeline ADC has a number of stages, e.g., N stages, coupled in series or cascade. Each stage is designed to produce one bit of an N-bit digital representation of an analog input signal. Details on known pipeline ADCs are provided in U.S. Pat. Pub. No. 2009/0289821 by Li et al, which is hereby incorporated by reference in its entirety.
Sample-and-hold amplifiers are known to be useful for capturing and storing an analog voltage sampled at a predetermined point in time, and can be applied to pipeline ADCs. Certain sample-and-hold amplifier arrangements are described, e.g., in U.S. Pat. Pub. 2009/0195315 by Chou et al, which is hereby incorporated by reference in its entirety. A known sample-and-hold amplifier (“SHA”) includes first and second sampling capacitors for functionality known as pre-charging, as described in U.S. Pat. No. 6,529,049 by Erhart et al., hereby incorporated by reference in its entirety. An analog voltage from an analog voltage source is stored on the sampling capacitors and is transferred to an input of an operational amplifier, e.g., a unity gain amplifier. The second sampling capacitor is enabled, e.g., by a coupling arrangement of switches, to pre-charge the input of the amplifier to a sampled analog voltage, which is achieved by the first sampling capacitor by known techniques. Provided that the sampled analog voltage stored on the first sampling capacitor is close to the pre-charged voltage already applied to the amplifier input by the second sampling capacitor, the error in the analog voltage provided at the output of the amplifier is reduced, and/or operation of the ADC is faster, compared to SHAs that do not employ pre-charging.
In a known pipeline ADC, a pre-charged SHA is combined with a pipeline ADC for sampling an analog input signal and converting it to digital format. Time interleaving is known in the art for processing data in the context of a pipeline ADC simultaneously on a number of channels. For example, for two data channels, a stage of a pipeline ADC according to a known technique is processed by two separate switched capacitor circuits in a circuit 100 shown in FIG. 1. A first switched capacitor circuit 110a and a second switched capacitor circuit 110b are both coupled to a sample-and-hold amplifier (SHA) 105 via input node 102. Switched capacitor circuit 110a has capacitors 131, 132, and operational amplifier 130a, and switched capacitor circuit 110b has capacitors 133, 134, and operational amplifier 130b. Switches 123a, 123b, 123c, 123d (123 generally) and switches 124a, 124b, 124c, 124d (124 generally) control a coupling arrangement between the capacitors 131, 132, 133, 134, input node 102, and operational amplifiers 130a and 130b. Switches 123a, 123b, 123c, and 123d are controlled by a first signal and thus open or close together. Switches 124a, 124b, 124c, and 124d also open or close together but are controlled by a second signal that is the complement of the first signal. Switched capacitor circuits 110a and 110b have two states. In a first state, switches 123 are closed and switches 124 are open, causing capacitors 131, 132, 133, and 134 to store the voltage corresponding to node 102. In a second state, switches 124 are closed and switches 123 are open, creating feedback loops including capacitors 131, 132, 133, 134 and operational amplifiers 130a, 130b. A multiplexer 180 selects between the outputs of operational amplifiers 130a and 130b based on a select signal SEL. Control circuitry to control switches 123 and 124 is not shown in FIG. 1. An output of multiplexer 180 may be converted by a digital to analog converter (DAC) 160 to analog signal that is provided as a reference voltage for switched capacitor circuits 110a and 110b. The output of multiplexer 180 may be passed to a next pipeline stage. The input signal at input node 102 is converted by a DAC 162 to analog signal VrDj. DACs 162 and 160 provide bit processing for a current pipeline stage and a next pipeline stage.